The present invention relates to the field of process automation and control, and, more particularly, to a device, system, and method for compensating for delays in a serial encoder interface circuit.
Encoders are measuring systems that can detect rotational and linear positions of machines such as servomotors, linear actuators, tachometers, and the like, which can allow accurate positioning of such machines, and determination of such quantities as velocity and acceleration. Encoders can be used in conjunction with control systems such as programmable logic control (PLC) and computer numerical control (CNC) systems, as well as various drive systems.
Many different types of encoders are available for such purposes. For example, a differentiation is frequently made between incremental and absolute encoders. Incremental encoders can generate a defined number of steps (increments) per revolution, which are processed in the control system. Absolute value encoders can provide, directly after the control system is powered-up, the absolute position value without the machine moving. The absolute position can be determined by opto-electronically scanning several code tracks. Single-turn encoders can sense the absolute position within a revolution, while multi-turn encoders, additionally can code the number of revolutions. Examples of applications for absolute encoders include machine tools, textile machinery, printing presses, wood working machines, handling technology, conveying and storage technology, and/or robotics.
The position information obtained by an encoder can be transferred to the control system via, for example, a Synchronous Serial Interface (SSI) or a drive bus. An SSI encoder circuit can utilize one or more gated clock pulse bursts, or even a stream of gated clock pulse bursts, to latch data regarding a current linear or rotational position of the machine and cause the position data to be shifted out of the encoder to a receiving shift register (a type of memory). The pulse bursts can enable the encoder to identify when to latch the position and when to shift each position bit to the receiving shift register. The clock generator also can send pulse bursts directly to the receiving shift register to identify when to expect position data from the encoder.
FIG. 1 is a logical circuit diagram of a known embodiment of an encoder interface circuit 100. Clock generator 110 can provide a gated clock pulse signal 101 through an isolation device 120, a driver 130, and a cable 140 to an encoder 150, such as an SSI encoder. Clock generator 110 also can provide a gated clock pulse signal 102 directly to receiving shift register 190 (a memory device). Upon receipt of an appropriate clock signal, position data 103 can be sent from encoder 150 through cable 160, receiver 170, and isolation device 180 to receiving shift register 190, which can accept the position data for further processing by a processor (not shown).
Many of the components of circuit 100 can have associated delays, which can be designated by the Greek symbol tau, but are herein designated by the Roman letter T with various subscripts. For example, isolation devices 120, 180 can have isolation delays Tj, driver 130 can have driver delay Td, cables 140, 160 can have cable delays Tc, encoder 150 can have a response time delay Te, receiver 170 can have a receiver delay Tr, and receiving shift register 190 can have a set-up time delay Tsu. Moreover, these delays can limit the responsiveness of the control and/or measurement system of which the circuit is a part. As pressures to increase the responsiveness of these systems rise, the impact of these delays becomes increasingly significant.
At least one exemplary embodiment of the present invention includes a method for compensating for delays in a circuit of a serial encoder. The method includes determining at least one delay associated with the circuit of the serial encoder. The method also includes adjusting an internal clock signal received by a data receiving memory associated with the serial encoder to account for the at least one determined delay.
At least one exemplary embodiment of the present invention includes a method for increasing a responsiveness of an encoder circuit. The method includes increasing a frequency of an internal clock signal for the encoder circuit in response to a predetermined delay of the internal clock signal as received by a data receiving memory of the encoder circuit.
At least one exemplary embodiment of the present invention includes a method for compensating for delays in a circuit of a serial synchronous interface (SSI) encoder interface. The method includes receiving a value of at least one delay associated with the circuit of the SSI encoder interface. The method also includes delaying a clock signal received by a data memory of the circuit by no more than the received delay value, and decreasing a period of the clock signal by no more than the received delay value.
At least one exemplary embodiment of the present invention includes a method for compensating for delays in a circuit of an absolute encoder interface. The method includes receiving a value of at least one delay associated with the circuit of the absolute encoder interface. The method also includes delaying a clock signal received by a data memory of the circuit by no more than the received delay value, and decreasing a period of the clock signal by no more than the received delay value.